The following documents are incorporated by reference herein:    [1] Mark Johnson, U.S. Pat. No. 5,629,549 (May 13, 1997).    [2] Mark Johnson, B. R. Bennett, P. R. Hammar and M. M. Miller, “Magnetoelectronic Latching Boolean Gate,” Solid State Electronics 44, 1099 (2000).    [3] A. Ney et al., Programmable Computing with a Single Magnetoresistive Element,” Nature 425, 485 (2003).    [4] P. Xu et al., “An All-Metal Logic Gate Based on Current-Driven Domain Wall Motion,” Nature Nanotech 3, 97 (2008).    [5] B. Behin-Aein et al., “Proposal for an All-Spin Logic Device with Built-in Memory,” Nature Nanotech 5, 266 (2010).    [6] J. Hong, M. Johnson et al., “Magnetic field controlled reconfigurable semiconductor logic,” published online in Nature, approximately Jan. 30 2013.
The existing technology for information processing is based on digital semiconductor electronics, dominated by Complementary Metal Oxide Semiconductor (CMOS) technology. The basic device is a Field Effect Transistor (CMOS FET), a planar, three terminal device comprising a source, drain, a channel connecting source and drain, and a gate. A gate voltage applied to the gate modulates the source-drain conductance, equivalently the conductance of the channel. Logical gates that perform basic Boolean operations on binary inputs of “0” or “1” are formed using arrangements of 4 to 8 FETs. The basic Boolean operations include AND, OR, NAND, NOR, XOR, and XNOR. More complex logic functions are built up using arrangements of the basic gates. High speed memory cells, Static Random Access Memory (SRAM), also are formed using arrangements of 4 to 8 FETs. Another kind of high speed memory, called a “flip-flop” or a “latch” memory, can be formed from a different arrangement of FETs. A combination of FETs can be arranged to form an on/off or “pass” switch. One example, a tri-state buffer, can pass a “0” or a “1” or it can disconnect its output from the output line. A tri-state buffer (also called an “on (pass)/off” switch) allows multiple outputs to connect to a single wire, permitting only one of them to drive a binary “0” or “1” onto the line.
A CMOS FET is an active device. It is connected to a supply voltage (typically called VDD) and a ground. The FET dissipates power during operation. When idle, the FET dissipates quiescent power in proportion to its characteristic leakage current. Any CMOS logic operation begins by supplying power to the circuit and all CMOS FETs dissipate power at any time that power is supplied. When power to the circuit is removed, all results of the logic operations are is erased unless a separate operation has been used to write the results to a separate memory array, either on- or off-chip. These kinds of logic circuits and operations can be called “volatile” logic, and volatile logic dissipates quiescent power.
FIG. 4 is a block diagram of a prior art microprocessor, adapted from the article “How Microprocessors Work,” by Marshall Brain [http://computer.howstuffworks.com/microprocessor2.htm/]. This represents the architecture of existing logic circuits (prior art), based on FETs. The combinations of devices introduced above form the elements (boxes) in the microprocessor diagram. The detailed operation of logic circuits is not necessary for an understanding of the invention. An introduction and general discussion of a microprocessor may be beneficial and is provided in the following remarks.
The microprocessor represented in FIG. 4 may be a simple unit for simple operations. It may also represent a more complicated unit such as the central processing unit (CPU) of a computer or computing system. The Clock is typically separate from the microprocessor, and there is a separate memory area (on- or off-chip) connected to the processor by one or more bus lines. The ALU is the Arithmetic Logic Unit and it performs binary logic operations. The Instruction Decoder accepts commands from a program (for example, it may retrieve a program from memory), translates the command to binary instructions and operations that can be performed at a low, granular level (sometimes called “machine language”), and controls the individual components of the microprocessor. In the simplest case, the ALU performs one of the basic Boolean operations AND, OR, NAND, NOR, NOT, XOR, XNOR, and operates on single bits. At a slightly higher level, the ALU might be a half adder. A slightly higher level would be a full adder operating on 8 bits. At a rather high level, the ALU might perform addition, subtraction, multiplication and division of n-bit numbers. For a simple example, it may be helpful to think of a basic Boolean operation on two bits, stored in Registers A and B (“flip-flop” or “latch” memory), with the output stored in Register C. In FIG. 4, black lines represent lines that pass data (also called bus lines).
The Instruction decoder has a control line to each element in the microprocessor (gray lines in FIG. 4). These control lines send instructions. For example, the Instruction decoder may send the following instructions:                Tell the A register to latch (store) the value currently on the data bus.        Tell the B register to latch the value currently on the data bus.        Tell the C register to latch the value currently output by the ALU.        Tell the program counter register to latch the value currently on the data bus.        Tell the address register to latch the value currently on the data bus.        Tell the instruction register to latch the value currently on the data bus.        Tell the program counter to increment.        Tell the program counter to reset to zero.        Activate an On (pass)/Off switch, allowing data to pass through (default is Off, an open circuit).        Tell the ALU what operation to perform.        Tell the test register to latch the test bit from the ALU (e.g. for comparison at later step).        Activate the Read line.        Activate the Write line.        
The Instruction decoder can receive bits of data from the Test Register and the Instruction Register. It is driven by the Clock and can be reset by external command.
Any instruction is implemented as a series of bit patterns, and a set of instructions is a program. The Instruction decoder may receive a program by reading it from memory, or it may receive a program from external input. The Instruction decoder has a list of basic instructions stored in “read only memory” (ROM), and it translates lines of program memory to lines of basic instructions. Simple instructions are coded as words in “Assembly” language. Some examples of simple instructions are given below. In the following, “address” may refer to an external address, such as an address on a different chip or a different sector (e.g. memory). “Address” may also refer to one of the elements in the microprocessor, or to a specific line in the program.                LOADA mem# Load register A with the binary value in memory address        “mem#”        The sequence of low-level instructions would be:                    send “mem#” to address register (from Instruction Register)            activate On/Off switch to open line to Address bus line            activate read line (data in address register “mem#” is sent to Data bus)            activate On/Off switch to open “Data in” line to Data bus            activate On/Off switch to open Register A            data is sent to Register A and latched (stored)                        LOADB mem# Load register B with the binary value in address “mem#”        CONB const Load constant value “const” into register B [similar for register A]        SAVEA mem# Save the binary value in register A to address “mem#” [similar for registers B, C]        ADD Add the values in registers A and B and store the result in register C        SUB Subtract the values in registers A and B and store the result in register C        MUL Multiply the values in registers A and B and store the result in register C        DIV Divide the values in registers A and B and store the result in register C        COM Compare the values in registers A and B and store the result in register C        JUMP addr# Jump to address “addr#”        JEQ addr# If equal, jump to address “addr#”        JNEQ addr# If not equal, jump to address “addr#”        JG addr# If greater than, jump to address “addr#”        JGE addr# If greater than or equal to, jump to address “addr#”        JL addr# If less than, jump to address “addr#”        JLE addr# If less than or equal to, jump to address “addr#”        STOP Stop execution        
As another example of a simple operation, the ADD instruction would require the following set of signals from the Instruction decoder:    First clock cycle: (load the instruction)            Activate the On/Off switch for the program counter        Activate the Read line        (the current program line address is sent to memory)        Activate the On/Off switch for the data-in line        Read the instruction into the Instruction Register            Second clock cycle: (decode the ADD instruction)            set the ALU operation to addition        send the output of the ALU to Register C and store (latch)            Third clock cycle: (increment program counter)            send increment command from Instruction Decoder to Program counter        
According to the prior art represented by FIG. 4, all of the digital electronic devices and structures represented with blocks are active devices. They draw power from a power supply at a specified voltage (called VDD for CMOS, as mentioned above). For the microprocessor to operate, a power supply is switched ON and all the elements inside the heavily dotted lines in FIG. 4 draw power. They continue to draw power until the power supply is switched OFF, at which time the results of all logic processes are erased unless they have been stored to a separate nonvolatile storage chip or device. As noted above, the Clock is continuously powered and may reside on the processor chip or may be a separate, stand-alone unit.